The present invention relates to a semiconductor integrated circuit and a method for testing the same and, more particularly, to a semiconductor integrated circuit and a test method which are suitable for a GHz-class high-speed I/O interface.
Along with the recent increase in speed of the input/output interface of a semiconductor integrated circuit, a demand has arisen for processing signals in a GHz band.
FIG. 6 shows the arrangement of a transmitter (TX) 50, receiver (RX) 51, and PLL (Phase Locked Loop) 52 used in an input interface.
The transmitter 50 receives low-speed parallel transmission data, converts the data into high-speed serial data, and outputs the converted data.
The receiver 51 receives high-speed serial reception data, converts the data into low-speed parallel data, and outputs the converted data to a data processing circuit (not shown).
The transmitter 50 and receiver 51 use the common PLL 52 as a clock source.
The receiver 51, transmitter 50, and PLL 52 are incorporated in a single chip. A reference frequency source 53 which generates a reference frequency to be used by the PLL 52 is arranged outside the chip.
FIG. 7 shows the arrangement of a clock data recovery (to be referred to as a CDR hereinafter) circuit included in the receiver 51.
The receiver 51 comprises a phase comparator 61, serial/parallel converter 62, digital filter 63, control circuit 64, and phase interpolator 65.
The phase comparator 61 retimes (samples) input data by a recovery clock. Simultaneously, the phase comparator 61 determines whether the phase relationship between the recovery clock and the input data advances or delays from an optimum value. When the phase advances from the optimum value, a down signal is output together with the recovery data. When the phase delays from the optimum value, an up signal is output together with the recovery data.
The serial/parallel converter 62 receives the recovery data and the up or down signal from the phase comparator 61 and converts the data into a low-speed parallel signal.
The digital filter 63 averages the paralleled up or down signals output from the serial/parallel converter 62, compares the number of up signals with the number of down signals at a predetermined time interval, and sends the up or down signal to the control circuit 64, when the accumulated numbers of paralleled up or down pulses reaches the pre-determined threshold value.
The control circuit 64 receives the up or down signal, generates a control signal to decide the mixing ratio of clocks with different phases, and supplies the control signal to the phase interpolator 65.
The phase interpolator 65 receives the control signal output from the control circuit 64 and a reference clock signal with a phase of 0° or 90° output from the PLL 52. The phase interpolator 65 generates clock signals of 180° and 270° inside, mixes the clocks with different phases on the basis of the control signal to generate a clock signal (to be referred to as a recovery clock hereinafter) having a specific phase, and outputs the clock signal to the phase comparator 61.
As described above, the CDR circuit is a negative feedback loop circuit. A recovery clock phase with which the phase relationship between the data input to the phase comparator 61 and the recovery clock has the largest margin can be generated.
Such a CDR circuit is required to have a capability for normally recovering data even when the frequency value of the bit rate of input data and that of the reference clock signal supplied from the PLL 52 have a difference, namely a transmitter and the CDR are plesiochronous operation.
A case will be examined in which a chip having a transmitter 50a, receiver 51a, and PLL 52a and a chip having a transmitter 50b, receiver 51b, and PLL 52b are separately prepared, as shown in FIG. 8. Assume that reference clocks having different frequencies fref1 and fref2 are supplied from different reference frequency sources to the PLLs 52a and 52b. Data received by the receiver 51a is transmitted by the transmitter 50a and received by the receiver 51b. In addition, data transmitted by the transmitter 50b is received by the receiver 51a and transmitted by the transmitter 50a. 
In this case, the bit rate of input data and the clock signal supplied from the PLL 52a or 52b have a frequency difference.
Before shipment of transmitters/receivers, the capability for absorbing such a frequency difference must be tested.
To do this test, the clock signal on the transmitter side and that on the receiver side must have a frequency difference.
In the transmitter/receiver having the arrangement shown in FIG. 6, the transmitter 50 and receiver 51, which are mounted on the same chip, shares the single PLL 52. For this reason, no clock signals having a frequency difference can be generated, and the test cannot be executed.
Conventionally, the test must be executed by connecting two transmitters/receivers having different reference frequency sources.
However, this test method is not suitable for mass production because it is time-consuming, and it is difficult to control the frequency difference between the two reference frequency sources.
As another test method executed without connecting different chips, there is a loop back test method which makes it possible to input the output signal from the transmitter 50 in the same chip to the receiver 51 by switching an external signal, as shown in FIG. 9.
However, even when the loop back test method is used, the transmitter 50 and receiver 51 in the same chip use the same clock frequency, as described above. Hence, no data transmission/reception test can be executed assuming that the transmitter 50 and receiver 51 have a frequency difference.
As described above, conventionally, it is difficult to execute a data transmission/reception test assuming that the transmitter and receiver use clock signals having different frequencies.